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LM8207 Fiches technique(PDF) 21 Page - National Semiconductor (TI) |
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LM8207 Fiches technique(HTML) 21 Page - National Semiconductor (TI) |
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21 / 22 page ![]() Application Section (Continued) LAYOUT RECOMMENDATIONS A proper layout is necessary for optimum performance of the LM8207. A low impedance and clean ground plane is rec- ommended. The traces from the V SS pin to the ground plane should be as short as possible. Decoupling capacitors should be placed very close to the V DD pin. Connections of these decoupling capacitors to the ground plane should be very short. An additional decoupling capacitor for OUT_V REF is recommended. Due to the heavy current peaks and short transitions at the V COM node, traces from the output of the VCOM buffer should be low impedance and as short as possible, to minimize both voltage drops over the trace and unwanted EM distur- bances. Bottom View 20137951 FIGURE 14. Layout of LM8207 Evaluation Board (Actual Size) TOP View 20137952 FIGURE 15. Layout of LM8207 Evaluation Board (Actual Size) www.national.com 21 |
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