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STM32MP151AAB3 Fiches technique(PDF) 34 Page - STMicroelectronics

No de pièce STM32MP151AAB3
Description  Arm® Cortex®-A7 800 MHz Cortex®-M4 MPU, TFT, 35 comm. interfaces, 25 timers, adv. analog
PDF  253 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32MP151AAB3 Fiches technique(HTML) 34 Page - STMicroelectronics

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Functional overview
STM32MP151A/D
34/253
DS12500 Rev 3
Figure 3. STM32MP151A/D bus matrix
MSv47456V2
MCU_AHB2
MCU_AHB_MPU
MCU_AHB_RET
MCU_AHB3
MCU_AHB_MEM2
MCU_AHB4
MCU_AHB_MEM1
MCU_AHB_MEM0
MPU_AXI_FMC
MPU_AXI_QUADSPI
MPU_AXI_SYSRAM
MPU_AXI_DDR1
MPU_AHB_MCU
MPU_AHB6
MPU_AXI_ROM
MPU_AHB5
MPU_APB5
MPU_AXI_STM
MPU_AXI_DDR2
MPU_DBG_APB
Interconnect AHB 32 bits 209 MHz - 7 masters / 9 slaves
NIC-400 AXI 64 bits 266 MHz - 10 masters / 12 slaves
FMC/NAND
DDRCTRL 533 MHz
APB bridge to APB5
APB bridge to DBG APB
QUADSPI
SYSRAM 256 KB
ROM 128 KB
STM
AHB bridge to AHB5
AHB bridge to AHB6
S1
S2
S3
S4
S5
S6
S7
S9
S10
S8
S0
S11
AHB 32 synchronous master port
AXI 64 synchronous master port
AXI 64 synchronous slave port
AXI 64 asynchronous master port
AXI 64 asynchronous slave port
AHB 32 synchronous slave port
AHB 32 asynchronous master port
AHB 32 asynchronous slave port
Masters access S0 XOR S1 layer
Default
slave
M0
M1
M2
M3
M4
M5
M6
M7
M9
M10
AXIMC
To MCU interconnect
Bridge to AHB3
Bridge to AHB2
RetentionRAM
Bridge to AHB4
SRAM3
S1
S2
S3
S4
S5
S6
S7
S0
M1
M2
M3
M4
M5
M6
M0
To MPU interconnect
SRAM1
SRAM2
M7
M8
M9
MCU_AHB_MEM3
SRAM4
S8



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