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M95M04-DR Fiches technique(PDF) 20 Page - STMicroelectronics

No de pièce M95M04-DR
Description  4-Mbit serial SPI bus EEPROM
PDF  46 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95M04-DR Fiches technique(HTML) 20 Page - STMicroelectronics

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Instructions
M95M04-DR
20/46
DS12179 Rev 1
to 1, the relevant memory area (as defined in Table 3) becomes protected against Write
(WRITE) instructions. The Block protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status register Write Disable (SRWD) bit is operated in conjunction with the Write
protect (W) signal. The Status register Write Disable (SRWD) bit and Write protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
register Write Disable (SRWD) bit is set to 1, and Write protect (W) is driven low). In this
mode, the non-volatile bits of the Status register (SRWD, BP1, BP0) become read-only bits
and the Write Status register (WRSR) instruction is no longer accepted for execution.
Table 6. Status register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status register Write protect
Block protect bits
Write enable latch bit
Write in progress bit



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