74V2T70 datasheet(1/7 Pages) STMICROELECTRONICS

No de pièce	74V2T70

Description	TRIPLE BUFFER

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Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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1/7

June 2003

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HIGH SPEED: tPD = 3.6ns (TYP.) at VCC =5V

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LOW POWER DISSIPATION:

ICC =1µA(MAX.) at TA =25°C

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COMPATIBLE WITH TTL OUTPUTS:

VIH =2V (MIN), VIL =0.8V (MAX)

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POWER DOWN PROTECTION ON INPUT

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SYMMETRICAL OUTPUT IMPEDANCE:

|IOH|= IOL =8mA (MIN) at VCC =4.5V

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BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

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OPERATING VOLTAGE RANGE:

VCC(OPR) = 4.5V to 5.5V

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IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74V2T70 is an advanced high-speed CMOS

TRIPLE BUFFER fabricated with sub-micron

silicon gate and double-layer metal wiring C2MOS

technology.

The internal circuit is composed of 2 stages

including buffer output, which provide high noise

immunity and stable output.

Power down protection is provided on input and 0

to 7V can be accepted on input with no regard to

the supply voltage. This device can be used to

interface5V to3V.

74V2T70

TRIPLE BUFFER

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES

PACKAGE

T & R

SOT23-8L

74V2T70STR

SOT23-8L

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