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87C196KB Fiches technique(PDF) 14 Page - Intel Corporation |
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87C196KB Fiches technique(HTML) 14 Page - Intel Corporation |
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14 / 22 page ![]() 8XC196KB/8XC196KB16 HOLD/HLDA Timings Symbol Description Min Max Units Notes THVCH HOLD Setup 55 ns (Note 1) TCLHAL CLKOUT Low to HLDA Low 15 ns TCLBRL CLKOUT Low to BREQ Low 15 ns THALAZ HLDA Low to Address Float 10 ns THALBZ HLDA Low to BHE, INST, RD,WR Float 10 ns TCLHAH CLKOUT Low to HLDA High b 15 15 ns TCLBRH CLKOUT Low to BREQ High b 15 15 ns THAHAX HLDA High to Address No Longer Float b 15 ns THAHAV HLDA High to Address Valid 0 ns THAHBX HLDA High to BHE, INST, RD,WR No Longer Float b 20 ns THAHBV HLDA High to BHE, INST, RD,WR Valid 0 ns TCLLH CLKOUT Low to ALE High b 515 ns NOTE : 1. To guarantee recognition at next clock. Maximum Hold Latency Bus Cycle Type Latency Internal Access 1.5 States 16-Bit External Execution 2.5 States 8-Bit External 4.5 States 270909±9 14 |
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