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GD25Q127CSES Fiches technique(PDF) 20 Page - GigaDevice Semiconductor (Beijing) Inc.

No de pièce GD25Q127CSES
Description  3.3V Uniform Sector Dual and Quad Serial Flash
PDF  79 Pages
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Fabricant  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
Site Internet  http://www.gigadevice.com/
Logo GIGADEVICE - GigaDevice Semiconductor (Beijing) Inc.

GD25Q127CSES Fiches technique(HTML) 20 Page - GigaDevice Semiconductor (Beijing) Inc.

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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25Q127C
20
Hardware Protected Mode is entered.
Figure7. Write Status Register Sequence Diagram
7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit is latched-in on the
rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max
frequency fR, during the falling edge of SCLK. Then the memory content at that address is shifted out on SO. The first byte
addressed can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read
Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects
on the cycle that is in progress.
Figure8. Read Data Bytes Sequence Diagram
Command
0
1
2
3
4
5
6
7
01H/31H/11H
CS#
SCLK
SI
SO
High-Z
8
9 10 11 12 13 14 15
MSB
7
6
5
4
3
2
1
0
Status Register in
Command
0
1
2
3
4
5
6
7
03H
CS#
SCLK
SI
SO
High-Z
8
9 10
28 29 30 31 32
MSB
3
2
1
0
34 35 36 37
33
23 22 21
7
6
5
4
3
2
1
0
38 39
24-bit address
MSB
Data Out1
Data Out2



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