| Moteur de recherche de fiches techniques de composants électroniques |
|
GD25Q127CFJS Fiches technique(PDF) 45 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
|
|||||||||||||||||||||||||||||
GD25Q127CFJS Fiches technique(HTML) 45 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
45 / 79 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q127C 45 8. ELECTRICAL CHARACTERISTICS 8.1. POWER-ON TIMING Figure 42. Power-on Timing Sequence Diagram Vcc(max) Vcc(min) VWI tVSL Chip Selection is not allowed Device is fully accessible Time Table 8.1. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min Max Unit tVSL VCC (min) To CS# Low 2.5 ms VWI Write Inhibit Voltage 1.5 2.5 V 8.2. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register bits are set to 0, except DRV1 bit (S22) is set to 1. 8.3. ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Ambient Operating Temperature -40 to 85 -40 to 105 -40 to 125 ℃ Storage Temperature -65 to 150 ℃ Applied Input/Output Voltage -0.6 to VCC+0.4 V Transient Input/Output Voltage (note: overshoot) -2.0 to VCC+2.0 V VCC -0.6 to 4.2 V |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |