CS4344/5/6/8

DS613PP2

13

4.2.2 Internal Serial Clock Mode

In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK

and LRCK. The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format.

Operation in this mode is identical to operation with an external serial clock synchronized with LRCK.

This mode allows access to the digital de-emphasis function. Refer to Figures 7 - 12 for details.

LR C K

SC L K

Le ft C h a n nel

Rig h t Ch a n n e l

SD A T A

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

Internal SCLK Mode

External SCLK Mode

MCLK/LRCK = 1024, 512, 256, 128, or 64

MCLK/LRCK = 768, 384, 192, or 96

MCLK/LRCK = 1152

Data Valid on Rising Edge of SCLK

LR C K

SC L K

Le ft C h a n nel

Rig h t Ch a n n e l

SD A T A

+3 +2 +1 LS B

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LS B

+5 +4

MSB -1 -2 -3 -4

Internal SCLK Mode

External SCLK Mode

Left Justified, up to 24-Bit Data

INT SCLK = 64 Fs if

MCLK/LRCK = 1024, 512, 256, 128, or 64

INT SCLK = 48 Fs if

MCLK/LRCK = 768, 384, 192, or 96

INT SCLK = 72 Fs if

MCLK/LRCK = 1152

Left Justified, up to 24-Bit Data

Data Valid on Rising Edge of SCLK

Figure 8. CS4345 Data Format (Left Justified)