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CS42406 Fiches technique(PDF) 23 Page - Cirrus Logic

No de pièce CS42406
Description  24-BIT, 192kHz 2-IN 6-OUT AUDIO CODEC
PDF  50 Pages
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Fabricant  CIRRUS [Cirrus Logic]
Site Internet  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS42406 Fiches technique(HTML) 23 Page - Cirrus Logic

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CS42406
23
SWITCHING CHARACTERISTICS - ADC SERIAL AUDIO PORT Logic “0” = GND =
0 V; Logic “1” = VLS, CL = 20 pF.
NOTE: Certain parameters depend on the 256x/384x (pin6) mode setting and are separated below.
Parameter
Symbol
Min
Typ
Max
Unit
MCLK Duty Cycle
45
-
55
%
Master Mode
ADC_SCLK falling to ADC_LRCK
tmslr
-20
-
20
ns
ADC_SCLK falling to SDOUT valid
tsdo
0
-
32
ns
Slave Mode
Single-Speed*
ADC_LRCK Frequency
MCLK = 256, 384 Fs (÷1 or 1.5)
(Note 18)
MCLK = 512, 768 Fs (÷2 or 3)
Fs
Fs
4
43
-50
50
kHz
kHz
ADC_LRCK Duty Cycle
40
-
60
%
SDOUT valid before ADC_SCLK rising
tstp
10
-
-
ns
SDOUT valid after ADC_SCLK rising
thld
5-
-
ns
ADC_SCLK falling to ADC_LRCK edge
tslrd
-20
-
20
ns
Double-Speed*
ADC_LRCK Frequency
MCLK = 128, 192 Fs (÷1 or 1.5)
(Note 18)
MCLK = 256, 384 Fs (÷2 or 3)
Fs
Fs
50
86
-100
100
kHz
kHz
ADC_LRCK Duty Cycle
40
-
60
%
SDOUT valid before ADC_SCLK rising
tstp
10
-
-
ns
SDOUT valid after ADC_SCLK rising
thld
5-
-
ns
ADC_SCLK falling to ADC_LRCK edge
tslrd
-20
-
20
ns
Quad-Speed*
ADC_LRCK Frequency
(Note 18)
MCLK = 128 Fs (÷2 or 3)
Fs
172
-
200
kHz
ADC_LRCK Duty Cycle
40
-
60
%
SDOUT valid before ADC_SCLK rising
tstp
10
-
-
ns
SDOUT valid after ADC_SCLK rising
thld
5-
-
ns
ADC_SCLK falling to ADC_LRCK edge
tslrd
-8
-
8
ns



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