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NUC505-YO2G Fiches technique(PDF) 71 Page - Nuvoton Technology Corporation

No de pièce NUC505-YO2G
Description  ARM짰 Cortex짰-M4 32-bit Microcontroller
PDF  130 Pages
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Fabricant  NUVOTON [Nuvoton Technology Corporation]
Site Internet  http://www.nuvoton.com
Logo NUVOTON - Nuvoton Technology Corporation

NUC505-YO2G Fiches technique(HTML) 71 Page - Nuvoton Technology Corporation

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NUC505
July. 26, 2018
Page 71 of 130
Rev.1.08
─
Debug access to all memory and registers in the system, including access to
memory mapped devices, access to internal core registers when the core is
halted, and access to debug control registers even while SYSRESETn is asserted.
─
Serial Wire Debug Port (SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP)
debug access. But NUC505 only supports SW-DP.
─
Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and
code patches.
─
Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints,
data tracing, and system profiling.
─
 Bus interfaces:
─
Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode,
and System bus interfaces.
Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface.
─
Bit-band support that includes atomic bit-band write and read operations.
─
Memory access alignment.
─
Write buffer for buffering of write data.
─
Exclusive access transfers for multiprocessor systems.



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