STC89C53RC datasheet(85/165 Pages) STC

85 / 165 page

Note that if an interrupt of higher priority level goes active prior to rising edge of the third machine cycle, then

in accordance with the above rules it will be vectored to during the fifth and sixth machine cycle, without any

instruction of the lower priority routine having been executed.

Thus the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the

appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases

it doesn’t. It never clears the Serial Port flags. This has to be done in the user’s software. It clears an external

interrupt flag (IE0 or IE1) only if it was transition-activated. The hardware-generated LCALL pushes the contents

of the Program Counter onto the stack (but it does not save the PSW) and reloads the PC with an address that

depends on the source of the interrupt being vectored to, as shown be low.

Source

Vector Address

IE0

0003H

TF0

000BH

IE1

0013H

TF1

001BH

RI+TI

0023H

TF2+EXF2

002BH

IE2

0033H

IE3

003BH

Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs

the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and

reloads the Program Counter. Execution of the interrupted program continues from where it left off.

Note that a simple RET instruction would also have returned execution to the interrupted program, but it would

have left the interrupt control system thinking an interrupt was still in progress.

6.5 External Interrupts

There are four external interrupt sources in STC89xx MCU. The external sources can be programmed to be level-

activated or transition-activated by clearing or setting bits IT0, IT1, IT2 or IT3 in Registers TCON or XICON. If

ITx=0, external interrupt x is triggered by a detected low at the INTx pin. If ITx=1, external interrupt x is edge-

triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle,

interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt.

Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at

least 12 system clocks to ensure sampling. If the external interrupt is transition-activated, the external source has

to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle to

ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by

the CPU when the service routine is called.

If the external interrupt is level-activated, the external source has to hold the request active until the requested

interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is

completed, or else another interrupt will be generated.

STC89C53RC Fiches technique(PDF) 85 Page - STCmicro Technology Co,.Ltd

STC89C53RC Fiches technique(HTML) 85 Page - STCmicro Technology Co,.Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL