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XUJ736125X Fiches technique(PDF) 1 Page - Integrated Device Technology |
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XUJ736125X Fiches technique(HTML) 1 Page - Integrated Device Technology |
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1 / 21 page ![]() 1 ©2018 Integrated Device Technology, Inc. June 25, 2018 De sc ript ion The XU devices are low phase noise quartz-based PLL oscillators supporting a large range of frequencies and output interface types. These devices are designed to operate at three different power supplies and are available in multiple package sizes as well as temperature grades. With a patented one-time program (OTP) allowing for infinite memory shelf life, the XU devices can be programmed to generate an output frequency from 16kHz to 1500MHz with a resolution as low as 1Hz accuracy. The configuration capability of this family of devices allows for fast delivery times for both sample and large production orders. Fe a t ure s ▪ Frequency range: 0.016MHz to 1500MHz ▪ Output types: LVDS, LVPECL, HCSL, LVCMOS ▪ Supply voltage options: 1.8V, 2.5V, or 3.3V ▪ Phase jitter (1.875MHz to 20MHz): 100fs typical ▪ Phase jitter (12kHz to 20MHz): 300fs typical ▪ Package options: — 5.0 × 3.2 × 1.2 mm — 7.0 × 5.0 × 1.3 mm ▪ Operating temperature: -20°C to +70°C — Frequency stability options: ±20, ±25, ±50, or ±100 ppm ▪ Operating temperature: -40°C to +85°C — Frequency stability options: ±25, ±50, or ±100 ppm ▪ Operating temperature: -40°C to +105°C — Frequency stability options: ±50 or ±100 ppm 1 2 3 4 5 6 E/D / NC NC / E/D OUT OUT2 VDD GND Pin Assignm e nt s T a ble 1 . 6 -pin Pa c k a ge Pin # Pin Name Description 1 2 3 4 E/D NC OUT NC VDD GND T a ble 2 . 4 -pin Pa c k a ge Pin # Pin Name Description [a] Pulled high internally = output enabled. [b] Low = output disabled. See Ordering Information for more details. 1 E/D NC Enable/Disable [a,b] No connect 2 NC E/D No connect Enable/Disable [a,b] 3 GND Connect to ground 4OUT Output 5 OUT2 Complementary output 6VDD Supply voltage 1 E/D Enable/Disable [a,b] 2 GND Connect to ground 3OUT Output 4VDD Supply voltage X U Da t a she e t X U Fa m ily of Low Pha se N oise Qua rt z-ba se d PLL Osc illa t ors |
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