14

Integrated

Circuit

Systems, Inc.

ICS950602

0469B—12/18/02

Power Down Waveform

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all

the output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

VCO Internal

0ns

12

25ns

50ns

CPU 100MHz

3.3V 66MHz

PCI 33MHz

APIC 16.7MHz

PD#

SDRAM 100MHz

REF 14.318MHZ

48MHZ