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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM652X Fiches technique(PDF) 213 Page - Texas Instruments |
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AM652X Fiches technique(HTML) 213 Page - Texas Instruments |
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213 / 299 page  CPTS_TS_COMP T6 T7 CPTS_TS_SYNC T8 T9 CPTS_SYNC_OUT T10 T11 213 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated (1) P = functional clock period in ns. Figure 5-91. CPTS Output Switching Characteristics 5.11.5.18 OSPI For more details about features and additional description information on the device Octal Serial Peripheral Interface, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. 5.11.5.18.1 OSPI with Data Training Table 5-86. OSPI Switching Characteristics - Data Training PARAMETER DESCRIPTION MODE MIN MAX UNIT tc(CLK) Cycle time, CLK DDR, 1.8V 6.02 ns DDR, 3.3V 7.52 ns tc(CLK) Cycle time, CLK SDR, 1.8V 5.00 ns SDR, 3.3V 7.52 ns 5.11.5.18.2 OSPI without Data Training NOTE The I/O Timings provided in this section are only applicable when data training is not implemented. Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL Delays are configured as described in Table 5-91 found in this section. Table 5-87, Table 5-88, Figure 5-92, and Figure 5-93 present switching characteristics for OSPI DDR and SDR Mode. Table 5-87. OSPI Switching Characteristics - DDR Mode (1) NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O1 tc(CLK) Cycle time, CLK 1.8V 19 ns 3.3V 19 ns O2 tw(CLKL) Pulse duration, CLK low -0.3+0.475*P (2) ns O3 tw(CLKH) Pulse duration, CLK high -0.3+0.475*P (2) ns |
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