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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM652X Fiches technique(PDF) 187 Page - Texas Instruments |
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AM652X Fiches technique(HTML) 187 Page - Texas Instruments |
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187 / 299 page  HYPERBUS_TIMING_01 CK, CK# CS# D8/LFD8 D2 RWDS DQ[7:0] D9/LFD9 Command-Address Host drives DQ[7:0] and Memory drives RWDS CK and Data are center aligned Host drives DQ[7:0] and RWDS 39:32 31:24 23:16 15:8 7:0 47:40 Dn Dn Dn+1 Dn+1 A B A B D7/LFD7 D6/LFD6 D11/LFD11 D10/LFD10 D12/LFD12 D4 D12/LFD12 187 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Table 5-54. Timing Requirements for HyperBus Initialization NO. PARAMETER DESCRIPTION MIN MAX UNIT D1 tw(RESETn) RESETn Pulse Width 200 ns D2 tw(csL) Chip Select Pulse Width 1000 ns D3 td(RESETnH-csL) Delay time, RESETn inactive to CSn active 200.34 ns D4 td(csL-RWDSL) Delay time, CSn active to RWDS falling 115 ns Table 5-55. HyperBus 166 MHz Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT D5 tskn(rwdsX-dV) Input skew, RWDS transitioning to D0:D7 valid -0.46 0.46 ns D6 tc(clk/clkn) CLK period, CLK/CLKn 6 ns D7 tw(clk/clkn) Pulse width, CLK/CLKn 2.7 ns D8 tw(csIV) Pulse width, CS0 invalid between operations 6 ns D9 td(clkH-csL) Delay time, CS0 active to CLK rising/ CLKn falling -3.41 ns D10 td(clkL[LE]-csH) Delay time, last falling CLK/ rising CLKn edge to CS0 inactive 0.66 ns D11 td(clkX-rwdsV) Delay time, CLK transition to RWDS valid 1.01 2.02 ns D12 td(clkX-d[0:7]V) Delay time, CLK transitioning to D0:7 valid 0.84 2.2 ns Table 5-56. HyperBus 100 MHz Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT LFD5 tskn(rwdsX-dV) Input skew, RWDS transitioning to D0:D7 valid -0.81 0.81 ns LFD6 tc(clk) CLK period, CLK 10 ns LFD7 tw(clk) Pulse width, CLK 4.5 ns LFD8 tw(csIV) Pulse width, CS0 invalid between operations 10 ns LFD9 td(clkH-csL) Delay time, CS0 active to CLK rising -3.76 ns LFD10 td(clkL[LE]-csH) Delay time, last falling CLK edge to CS0 inactive 1.77 ns LFD11 td(clkX-rwdsV) Delay time, CLK transition to RWDS valid 2.05 3.24 ns LFD12 td(clkX-d[0:7]V) Delay time, CLK transitioning to D0:7 valid 1.87 3.41 ns Figure 5-58. HyperBus Timing Diagrams - Transmitter Mode |
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