LM2467 datasheet(36/43 Pages) NSC

36 / 43 page

Control Register Definitions (Continued)

Bits 15–9

These bits are reserved and should be set to zero.

Display Window 2 Column Width:

COLWIDTH2B3 (0x841F)

COLWIDTH2B2 (0x841E)

Window 2 Column Width - High Bytes

COL[31:16]

COLWIDTH2B1 (0x841D)

COLWIDTH2B0 (0x841C)

Window 2 Column Width - Low Bytes

COL[15:0]

Bits 31–0

These are the Display Window 2 Column Width 2x Enable Bits. These thirty-two bits correspond to columns 31–0

of Display Window 2, respectively. A value of zero indicates the column will have normal width (12 OSD pixels). A

value of one indicates the column will be twice as wide as normal (24 OSD pixels). For the double wide case, each

Character Font pixel location will be displayed twice, in two consecutive horizontal pixel locations. The user should

note that if more than 32 display characters are programmed to reside on a line, then all display characters after

the first thirty-two will have normal width (12 pixels).

Fade In/Fade Out Interval Register:

FADE_INTVL (0x8429)

Vertical Interval

Horizontal Interval

V_INTVL[3:0]

H_INTVL[3:0]

Bits 7–4

These three bits determine the interval for fading in or fading out the OSD window in the vertical

direction.

Bits 3–0

These three bits determine the interval for fading in or fading out the OSD window in the horizontal

direction.

Pre-Amplifier Interface Registers

Blue Channel Gain:

BGAINCTRL (0x8430)

Res’d

Blue Gain

BG[6:0]

Bits 6–0

This register determines the gain of the blue video channel. This affects only the blue channel

whereas the contrast register (0x8433) affects all channels.

Bit 7

Reserved and should be set to zero.

Green Channel Gain:

GGAINCTRL (0x8431)

Res’d

Green Gain

GG[6:0]

Bits 6–0

This register determines the gain of the green video channel. This affects only the green channel

whereas the contrast register (0x8433) affects all channels.

Bit 7

Reserved and should be set to zero.

Red Channel Gain:

RGAINCTRL (0x8432)

Res’d

Red Gain

RG[6:0]

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