CPC5902 datasheet(9/14 Pages) IXYS

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INTEGRATED CIRCUITS DIVISION

CPC5902

R03

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determined by tOPLH_AB. Side B deassertion occurs at

time tENDB given by:

tENDB = tENDA + tSLEWA + tOPLH_AB

Thus at Side B input, an applied pulse of less than

80ns is stretched to:

tPWB_min = tFIL + tOPHL_BA + tOPHL_AB + tOPLH_BA + tSLEWA + tOPLH_AB

which is typically 330ns. More importantly, only one

pulse is seen at both ports, with no extra or missing

clock or data edges, assuring line integrity.

Pulses of width larger than approximately 80ns

applied to the Side B input do not utilize the flip-flop to

terminate the pulse, but do need to propagate to

Side A and then back to Side B when returning high

after being asserted low. The Side A pulse width is

given by the usual pulse width distortion relation:

tPWA_nom = tPULSE + tPLH_BA - tPHL_BA

which is typically tPULSE + 75ns. Note that tPLH_BA and

tPHL_BA are observed at the external pins, and are

provided in the table, “Electrical Specifications” on

page 4. The pulse at Side B is asserted by an

external driver pulling low, and lasts for time tPULSE. At

the end of the pulse, the rising edge passes through

the internal filter with delay tFIL, then applied to the

LED and received at Side A tOPLH_BA later. After time

tSLEWA the output at Side A crosses the logic high

threshold causing the Side A LED drive to deactivate,

which propagates the deasserted state back to Side B

with a delay of tOPLH_AB. Thus normal-width pulses of

width tPULSE applied at Side B (IOB) exhibit a

stretched pulse width of:

tPWB_nom = tPULSE + tFIL + tOPLH_BA + tSLEWA + tOPLH_AB

at IOB, which is also given by:

tPWB_nom = tPULSE + tPHL_BAB

and is typically tPULSE + 290ns.

Side A receivers have been designed to exhibit a

significant amount of hysteresis, which helps to

eliminate false clocking. They have not been internally

low-pass filtered beyond the filtering inherent within

the optical channel. When the I2C bus is terminated

for maximum bandwidth (6mA pullups and minimal

capacitance), the receivers typically will respond to

pulses greater than 12ns. If additional filtering is

desired, then externally increasing the load

capacitance of the I2C lines until the amount of time

the offending signal spends above/below VDD /2 is

less than 10ns will reject the signal at the expense of

increasing rise and fall times.

Side B receivers do implement some hysteresis and

low-pass filtering in addition to the optics. An

asserted pulse typically needs to be held below

0.2VDD for 15ns before it is accepted at Side B input.

This may require a 30ns pulse applied by a typical

driver with just 20pF loading the I2C lines.

While any very short pulses stretched to the minimum

times above would seem to cause large amounts of

pulse width distortion, within 400kHz Fast-mode I2C

the shortest allowable signal or clock asserted low

time is 1.3

s. Neither Standard-mode nor Fast-mode

variants include any legal signals that are less than

80ns (typ); thus the tPWA_nom and tPWB_nom equations

above always apply. The pulse width on valid longer

pulses receives less stretching and is proportionally

less noticeable. For example the Fast-mode minimum

clock low time of 1.3

S when applied at Side B would

typically be seen as a 1.375

S pulse at Side A and will

be stretched to a length of 1.59

s for other devices on

the Side B bus.

Internal filtering and the flip-flop at Side B are used to

ensure that an equal number of pulse edges are seen

at both sides of the isolation barrier when Side B is

driven. When a signal at Side B is asserted low, the

flip-flop self-drives that Side B I/O pin until the optical

channel back from Side A proves that Side A has

successfully been asserted. While this is generally a

welcome error reduction feature and is especially

useful on the side with nonstandard levels, it does

need to be considered when assigning Side A and

Side B ports. If Side A is not powered up, then the

signal back from Side A will not appear until after

Side A has been powered, and the signal at Side B

will be stretched until that time. Side A uses filtered

hysteresis at its standard inputs, not pulse stretching,

to defeat sub-minimum-size pulses. Thus that side of

the isolation barrier, which will be the bus master at

power-up, should generally be assigned to Side A.

Note that the pinout of the package is rotationally

symmetrical. As a result, changing which side of the

isolation barrier utilizes Side A standard levels can be

accomplished by rotating the part 180° before it is

soldered onto the board.

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