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AD9520-1/PCBZ Fiches technique(PDF) 48 Page - Analog Devices

No de pièce AD9520-1/PCBZ
Description  12 LVPECL/24 CMOS Output Clock Generator
PDF  80 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9520-1/PCBZ Fiches technique(HTML) 48 Page - Analog Devices

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AD9520-1
Data Sheet
Rev. B | Page 48 of 80
12
3
4
5
6
7
8
910
INPUT TO VCO DIVIDER
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
1
11
12
13
14
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
Figure 52. SYNC Timing Pipeline Delay When the VCO Divider Is Used—CLK or VCO Is Input
INPUT TO CLK
INPUT TO CHANNEL DIVIDER
OUTPUT OF
CHANNEL DIVIDER
SYNC PIN
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
12
3
4
5
6
7
8
910
11
12
13
14
1
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
Figure 53. SYNC Timing Pipeline Delay When the VCO Divider Is Not Used—CLK Input Only



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