AD9577BCPZ-R7 datasheet(27/44 Pages) AD

No de pièce	AD9577BCPZ-R7

Description	Clock Generator with Dual PLLs, Spread Spectrum, and Margining

PDF	44 Pages

Scroll/Zoom	100%

Fabricant	AD [Analog Devices]

Site Internet	http://www.analog.com

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27 / 44 page

Data Sheet

AD9577

Rev. A | Page 27 of 44

DETAILED BLOCK DIAGRAM

XTAL

OSC

REFCLK

XT1

XT2

MARGIN

SSCG

MAX_BW

REFSEL

CMOS

AD9577

DIVIDE

1 OR 2

SCL

SDA

I2C

CONTROL

22pF

VCO

2.15GHz

2.55GHz

LDO1

DIVIDE BY

80 TO 131

FEEDBACK

DIVIDER

PLL1

DIVIDE BY

2 TO 6

DIVIDE BY

1 TO 32

LVPECL/LVDS

REFOUT

OR 2 × CMOS

FORMAT1

DIVIDE BY

2 TO 6

DIVIDE BY

1 TO 32

LVPECL/LVDS

OR 2 × CMOS

VCO

DIVIDERS

OUTPUT

DIVIDERS

OUTPUT

BUFFERS

VCO

2.15GHz

2.55GHz

LDO2

DIVIDE BY

80 TO 131

FEEDBACK

DIVIDER

PLL2

DIVIDE BY

2 TO 6

DIVIDE BY

1 TO 32

LVPECL/LVDS

OR 2 × CMOS

FORMAT2

DIVIDE BY

2 TO 6

DIVIDE BY

1 TO 32

LVPECL/LVDS

OR 2 × CMOS

SDM

VCO

DIVIDERS

OUTPUT

DIVIDERS

OUTPUT

BUFFERS

3-BIT

FRAC

FRAC_TRIWAVE

SSCG

MOD

fPFD

CKDIV

FRAC

FRACSTEP

NUMSTEPS

SSCG

TRIWAVE

GENERATOR

FRAC_TRIWAVE

220nF

LDO

4× GND +

PADDLE

14× VS

Figure 32. Detailed Block Diagram

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