CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

14

POST OFFICE BOX 655303

APPLICATION INFORMATION

LVPECL receiver input termination

The input of the CDCM1802 has high impedance and comes with a very large common mode voltage range.

For optimized noise performance it is recommended to properly terminate the PCB trace (transmission line).

Additional termination techniques can be found in the following application notes: SCAA062 and SCAA059.

http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=scaa062

http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=scaa059

IN

LVPECL

150 Ω

150 Ω

50 Ω

50 Ω

IN

CDCM1802

C

VBB

50 Ω

50 Ω

Figure 13. Recommended AC-Coupling LVPECL Receiver Input Termination

LVPECL

130 Ω

83 Ω

CDCM1802

50 Ω

50 Ω

130 Ω

83 Ω

Figure 14. Recommended DC-Coupling LVPECL Receiver Input Termination