PCA2002 datasheet(6/20 Pages) PHILIPS

6 / 20 page

2004 Jan 20

Philips Semiconductors

Product speciﬁcation

32 kHz watch circuit with programmable

output period and pulse width

PCA2002

Table 3

Description of word A bits

Table 4

Description of word B bits

General start up sequence

You must follow the next sequence to ensure the correct

operation at start up:

1. Apply the supply voltage to the circuit.

2. Wait at least two seconds.

3. Connect pin RESET to pin VDD for a minimum of 62 ms

(this activates the stop mode).

4. Disconnect pin RESET from pin VDD (this resets the

circuit to normal operating mode).

After this sequence the memory contents are read

immediately and the programmed options are set. This

sequence also resets all major circuit blocks and ensures

that they function correctly.

To ensure that the oscillator starts up correctly you must

execute a reset sequence (see Fig.5).

Programming procedure

For a watch it is essential that the timing calibration can be

made after the watch is fully assembled. In this situation,

the supply pins are often the only terminals which are still

accessible.

Writing to the OTP cells and performing the related

functional checks is achieved in the PCA2002 by

modulating the supply voltage. The necessary control

circuit consists basically of a voltage level detector, an

instruction state counter (which determines the function to

be performed) and an 8-bit shift register which allows

writing the OTP cells of an 8-bit word in one step and which

acts as data pointer for checking the OTP content.

BIT

VALUE

DESCRIPTION

Inhibit time

1to7

−

the number of the 8192 Hz pulses to

be removed (binary coded;

MSB = A1, LSB = A7)

Calibration period

1 minute

2 minutes

BIT

VALUE

DESCRIPTION

Pulse width tp (ms)

1 to 3

000

0.98

001

1.95

010

2.9

011

3.9

100

4.9

101

5.9

110

6.8

111

7.8

Output period (s)

4 to 6

000

001

010

011

100

Duty cycle of motor pulse

75 %

100 %

Pulse stretching

no pulse stretching

a pulse width of 2tp and a duty factor

of 25 % is added

VDD

VP(stop)

t(start) > 500 ms

VSS

VDD(nom)

001aaa285

tp(stop)

Fig.5 Supply voltage at start up.

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