LTC6255 datasheet(21/30 Pages) LINER

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LTC6752/LTC6752-1/

LTC6752-2/LTC6752-3/

LTC6752-4

6752fc

For more information www.linear.com/LTC6752

applicaTions inForMaTion

are tied to the output pins are cut off and cannot source/

sink any current. The shutdown pin needs to be taken to

within 600mV of the negative supply for the part to shut

down. When left floating, the shutdown pin is internally

pulled towards the positive supply, and the comparator

remains fully biased on.

Dispersion

Dispersion is defined as the change in propagation delay

for different input conditions. It becomes very crucial in

timing sensitive applications. Overdrive dispersion from

10mV overdrive to 125mV overdrive is typically less than

1.8ns(150mVtotalstepsize).ThegraphtitledPropagation

Delay vs Common Mode Voltage shows the dispersion

due to shifts in input common mode voltage.

Jitter

The LTC6752 family has been designed for low phase

noise and jitter. This allows it to be used in applications

where high frequency low amplitude sine waves need to

be converted to full-logic level square waves with mini-

mal additive jitter. The graph titled Output Jitter vs Input

Amplitude demonstrates the additive jitter of the LTC6752

family for different amplitudes of a sinusoidal input. Refer

totheElectricalCharacteristicstabletoseehowjittervaries

with signal frequency.

High Speed Board Design Techniques

Being very high speed devices, members of the LTC6752

family are prone to output oscillations if certain guidelines

are not followed at the board level. Low impedance supply

planes, especially for the VDD and VEE pins, help to reduce

supply bounce related oscillations. Supply bounce tends to

worsenathigheroutputsupplyvoltagesduetolargerswings

andhigheroutputcurrentdrivecapability.Parasiticfeedback

betweentheoutputandinputpinsshouldbeminimized.The

pinoutsoftheLTC6752familymembershavebeenarranged

to minimize parasitic feedback. Input and output traces on

the board should be placed away from each other. If that is

not possible a ground or supply trace should be used as a

guard to isolate them. If possible, a supply/ground trace that

is not directly connected to the supply pins of the device,

but rather directly connected to the supply terminal of the

board, should be used for such a purpose.

The positive supply pins should be adequately bypassed

to the VEE pin to minimize transients on the supply. Low

ESR and ESL capacitors are required due to the high speed

nature of the device. Even a few nanohenries of parasitic

trace inductance in series with the supply bypassing can

causeseveralhundredmillivoltsofdisturbanceonthesupply

pins during output transitions. A 2.2µF capacitor in parallel

withmultiplelowESL,lowESR100nFcapacitorsconnected

as close to the supply pins as possible to minimize trace

impedance is recommended. In many applications the VEE

pin will be connected to ground. In applications where the

VEE pin is not connected to ground, the positive supplies

shouldstillbebypassedtoVEE.TheVEEpinshouldalsothen

be bypassed to a ground plane with a 2.2µF capacitor in

parallel with low ESL, low ESR 100nF capacitors if possible.

For devices with separate positive input and output sup-

plies, capacitors should not be placed between the two

positive supplies; otherwise disturbances due to output

switching can couple back to the inputs.

Tominimizesupplybounce,theboardlayoutmustbemade

with careful consideration of the supply current return

paths. The output current will return back to the supply

via the lowest impedance path available. If the terminating

connection of the load is easily available on the board, VEE

should be bypassed to the terminating connection using

2.2µF and 100nF capacitors as described previously.

DuetothefastriseandfalltimesoftheLTC6752/LTC6752-1/

LTC6752-2/LTC6752-3/LTC6752-4,outputtracesshouldbe

shielded with a low impedance ground plane to minimize

electromagnetic interference. Due to the complementary

nature of its outputs, the LTC6752-3 can provide a first

order cancellation of EMI effects.

When the input slew rate is small, sustained oscillations

can occur at the output pin while the input is transitioning

due to even one millivolt of ground bounce. For applica-

tions where the input slew rate is low, internal hysteresis

should not be removed by taking the LE/HYST pin high,

as the addition of hysteresis makes the comparators more

immune to disturbances such as ground bounce. Increas-

ing hysteresis by adjusting the LE/HYST pin voltage or by

adding positive feedback as discussed in the section on

hysteresis can further improve noise immunity.

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