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AD6624AS/PCB Fiches technique(PDF) 6 Page - Analog Devices |
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AD6624AS/PCB Fiches technique(HTML) 6 Page - Analog Devices |
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6 / 40 page ![]() REV. 0 AD6624A –6– TIMING DIAGRAMS CLK LIA-A LIA-B LIB-A LIB-B tDLI tCLK tCLKL tCLKH Figure 1. Level Indicator Output Switching Characteristics RESET tSSF Figure 2. RESET Timing Requirements CLK IN[13:0] EXP[2:0] DATA tSI tHI Figure 3. Input Data Timing Requirements CLK SCLK tDSCLKH tSCLKH tSCLKL Figure 4. SCLK Switching Characteristics (Divide by 1) CLK SCLK tDSCLKH tSCLKL Figure 5. SCLK Switching Characteristic (Divide by 2 or EVEN Integer) CLK SCLK tDSCLKH tDSCLKLL Figure 6. SCLK Switching Characteristic (Divide by 3 or ODD Integer) SCLK SDFS SDI SDFE tSSI tHSI DATAn tDSDFE tDSDFS Figure 7. Serial Port Switching Characteristics |
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