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2

This parameter is sampled, but not 100% tested.

3

For test conditions, see AC Test Conditions, Figures A, B, and C.

5

This parameter is guaranteed, but not 100% tested.

6WE is High for read cycle.

7CE1 and OE are Low and CE2 is High for read cycle.

8

Address valid prior to or coincident with CE1 transition Low and CE2 transition High.

9

All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE1 or WE must be High or CE2 Low during address transitions. Either CE or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 CE1 and CE2 have identical timing.

13 2V data retention applies to the commercial operating range only.

14 C = 30pF, except on High Z and Low Z parameters, where C = 5pF.

Parameter

Symbol

Test conditions

Min

Max

Unit

CE1

CE2

2.0

–

V

Data retention current

–60

µA

Chip enable to data retention time

0–

ns

Operation recovery time

–ns

CE1

Data retention mode

CS2

-Output load: see Figure B or Figure C.

- Input pulse level: GND to 3.0V. See Figure A.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

10%

90%

10%

90%

GND

+3.0V

Figure A: Input pulse

2ns

255

Ω

480

Ω

GND

+5V

Figure B: 5V Output lo

DG

255

Ω

320

Ω

GND

+5V

Figure C: 3.3V Output load

168

Ω

Thevenin Equivalent:

+1.728V (5V)