SC2449 datasheet(15/20 Pages) SEMTECH

15 / 20 page

 2002 Semtech Corp.

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POWER MANAGEMENT

SC2449

Bias Generation

A 6-7 Volt supply voltage is required to power up the

SC2449. This voltage could be provided by an external

power supply or derived from VIN through an external

pass transistor. REGDRV is the control signal to the base

of the pass transistor that will regulate VCC. The voltage

at the VCC pin is compared to the internal voltage refer-

ence, and the REGDRV pin can sink up to 5mA current to

regulate the voltage at the VCC pin.

Enable

If the ENABLE pin is connected to logic high, the SC2449

is enabled, while connecting it to ground will put the de-

vice into disabled mode. The ENABLE pin can also be

configured as input UVLO through input voltage divider

resistors. The controller will be enabled when the EN-

ABLE pin voltage reaches 2.05 V, and will be disabled

with 400mV hysteresis.

Under Voltage Lockout

Under Voltage lockout (UVLO) circuitry senses VCC through

a voltage divider. If this signal falls below 5.8V, with a

typical hysteresis of 400 mV, the BG pin is pulled low by

an internal transistor causing the lower MOS.ET gate to

be on and the upper MOS.ET gate off for both phases.

Over Voltage Protection

The SC2449 provides OVP protection for each output

individually. Once the converter output voltage exceeds

120% nominal output voltage, the lower MOS.ET gates

are latched on and the upper MOS.ET gates are latched

off. The latch is then reset once the OVP condition is

removed.

Soft Start

An external capacitor at the BG pin is used to set up the

Soft Start duration. The capacitor value, in conjunction

with the internal 3K resistor at the BG pin, control the

duration to bring up the bandgap to its final level. As the

Theory of Operation (Cont.)

Over Current Protection

The SC2449 current limit provides protection during an

over current condition. A sense resistor or PCB trace

can be used to sense the input supply current.

The over current protection trip point is determined by

the voltage drop across the sense resistor. Once this

voltage drop exceeds the voltage across the program-

ming resistor (50µA through R26), OCP protection circuit

will be triggered. Due to component and layout parasitics,

filtering might be necessary across the OC+ and OC- pins.

It is recommended to use a small RC filter with time con-

stant around 0.2µS. To clean up the phase node ringing,

one usually has to have a ceramic capacitor from the

top .ET drain to the power ground. Too much capaci-

tance will bypass the top .ET current from the sensing

resistor hence reducing OCP accuracy, while to little ca-

pacitance will not be able to clean up the phase node

ringing for full load operation. See application circuits.

Once an over current condition occurs, the lower MOS.ET

gates are latched on and the upper MOS.ET gates are

latched off. The latch is then reset at the beginning of

the next clock cycle. The cycle is repeated indefinitely

until the over current condition is removed.

Thermal Shutdown

In addition to current limit, the SC2449 monitors over

temperature condition. The over temperature detection

will shut down the part if the SC2449 die temperature

exceeds 150°C, and will auto reset once the die tem-

perature is dropped down.

Gate Drive

The SC2449 integrates high current gate drivers for fast

switching of large MOS.ETs. The high-side gates can be

switched with peak currents of 1 Amp, while the larger

low-side gates can be switched with peak currents of 2

Amps. A cross conduction prevention circuitry ensures a

non-overlapping operation between the upper and lower

MOS.ETs. This prevents false current limit tripping and

provides high efficiency.

The switching frequency of each channel is one half of

the oscillator frequency. The oscillator clock is also avail-

able externally through the CLKOUT pin and can be used

to provide synchronization for other converters.

BG capacitor is being charged through the internal resis-

tor, the PWM pulse width increases until the bandgap is

charged completely. This controlled start up of the PWM

prevents output voltage overshoot, unnecessary com-

ponent stress, and noise generation during start up.

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