TUSB1002AI datasheet(9/31 Pages) TI1

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TUSB1002A

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SLLSF63 – MARCH 2018

Product Folder Links: TUSB1002A

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(1)

Following pins comprise CFG pins: MODE, CFG[2:1], CH1_EQ[2:1], CH2_EQ[2:1]

(2)

Internal reset is the logical AND of EN pin and internal power good.

6.6 Timing Requirements

over operating free-air temperature and voltage range (unless otherwise noted)

MIN

NOM

MAX

UNIT

td_pg

Internal power good asserted high when VCC is at 2.5V

µs

tCFG_SU

CFG(1) pins setup before internal Reset(2) high

µs

tCFG_HD

CFG(1) pins hold after internal Reset(2) high

500

µs

tVCC_RAMP

VCC supply ramp requirement

0.1

6.7 Switching Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tIDLEEntry

Delay from U0 to electrical idle

VCC = 3.0 V; EN = 1;See Figure 1

150

tIDLEEntry_U1

U1 exit time. Break in electrical idle

to transmission of LFPS.

VCC = 3.0 V; EN = 1; See Figure 1

150

tIDLEEntry_U2

U2/U3 exit time; Break in electrical

idle to transmission of LFPS

VCC = 3.0 V; EN = 1; See Figure 1

µs

tDIFF_DLY

Differential propagation delay

VCC = 3.0 V; EN = 1;

150

tPWRUP_ACTI

Time from assertion of EN to device

active and performing Rx.Detect on

both ports

VCC = 3.0 V; EN = 1;

tTX_RISE_FAL

Transmitter rise/fall time

VCC = 3.3 V; EN = 1; 10 Gbps; 20% to

80% of differential output; 1200 mVpp

linear range setting; Fast Input rise/fall

time;

tRF_MISMATC

Transmitter rise/fall mismatch

VCC = 3.3 V; EN = 1; 10 Gbps; 20% to

80% of differential output; 1200 mVpp

linear range setting; 1000 mVpp VID

tTX_DJ

Transmitter residual deterministic

jitter

VCC = 3.3 V; EN = 1; 10 Gbps; 1200

mVpp linear range setting; Input channel

loss of 12 dB; Output channel loss of 1.5

dB; Optimized EQ;

0.05

Figure 1. Idle Entry and Exit Latency

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