CY2VC511 datasheet(4/7 Pages) CYPRESS

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PRELIMINARY

CY2VC511

Document Number: 001-10796 Rev. *D

Page 4 of 7

Parameter Measurements

Figure 2. Output Duty Cycle Timing

Figure 3. Output Rise and Fall Time

DC Electrical Characteristics

Parameter

Description

Condition

Min

Typ

Max

Unit

IDD

Operating Supply Current

VDD = 3.465V, output unloaded

–

110

VOH

High Output Voltage

VDD = min, IOH = –4 mA

0.9*VDD

––

VOL

Low Output Voltage

VDD = max, IOL = 4 mA

–

0.1*VDD

VIH

Input High Voltage

For REFIN

1.25

–

1.8

VIL

Input Low Voltage

For REFIN

–

0.25

VVIN

VIN Input Voltage

–

VDD

IVIN

VIN Input Current

VSS ≤ VIN ≤ VDD

–10

–

μA

INLVIN

[3, 4]

VIN to FOUT Integral Nonlin-

earity

VSS ≤ VIN ≤ VDD

–1

–

AC Electrical Characteristics [3]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

FOUT

Output Frequency

–

MHz

Pull Range

VIN = VDD to VSS, relative to nominal fOUT

(VIN = 1.65V) across operating temperature and

supply voltage.

±115

–

ppm

TDC

Duty Cycle

Measured at VDD/2, defined in Figure 2

Output Rise Time

20% to 80% of VDD, CLOAD = 15 pF

–

0.7

1.5

Output Fall Time

80% to 20% of VDD, CLOAD = 15 pF

–

0.8

1.5

TLOCK

Start Up Time

Time for CLK to reach valid frequency measured

from the time VDD = VDD (min)

––

Note

3. Not 100% tested, guaranteed by design and characterization.

4. Integral nonlinearity is defined in IEEE Standard 1241-2000.

CLK

PERIOD

DC =

PERIOD

CLK

20%

80%

20%

80%

VDD

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