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AD8451

Data Sheet

BATTERY

VCTRL

SENSE

RESISTOR

ISVP

ISVN

BVP

BVN

MODE

SWITCHES

(3)

BATTERY

CURRENT

AVEE

BUFFER

CONSTANT

CURRENT LOOP

FILTER AMPLIFIER

–

1×

VINT

BUFFER

VSET

ISET

D C

VINT

ISMEA

BVMEA

–

AD8451

CONTROLLER

1×

SET

BATTERY

VOLTAGE

SET

BATTERY

CURRENT

EXTERNAL

PASSIVE

COMPENSATION

NETWORK

C = CHARGE

D = DISCHARGE

CONSTANT

VOLTAGE LOOP

FILTER AMPLIFIER

POWER CONVERTER

SWITCHED OR LINEAR

SYSTEM LOOP COMPENSATION

Figure 43. Signal Path of an Li-Ion Battery Formation and Test System Using the AD8451

INSTRUMENTATION AMPLIFIER (IA)

Figure 44 is a block diagram of the IA, which is used to monitor the

battery current. The architecture of the IA is the classic 3-op-amp

topology, similar to the Analog Devices industry-standard

AD8221 and AD620, with a fixed gain of 26. This architecture

provides the highest achievable CMRR at a given gain, enabling

high-side battery current sensing without the introduction of

significant errors in the measurement. For more information

about instrumentation amplifiers, see A Designer's Guide to

Instrumentation Amplifiers.

Reversing Polarity When Charging and Discharging

Figure 43 shows that during the charge cycle, the power converter

feeds current into the battery, generating a positive voltage across

the current sense resistor. During the discharge cycle, the power

converter draws current from the battery, generating a negative

voltage across the sense resistor. In other words, the battery current

polarity reverses when the battery discharges.

In the CC control loop, this change in polarity can be problematic

if the polarity of the target current is not reversed. To solve this

problem, the AD8451 IA includes a multiplexer preceding its

inputs that inverts the polarity of the IA gain. This multiplexer

is controlled via the MODE pin. When the MODE pin is logic

high (charge mode), the IA gain is noninverting, and when the

MODE pin is logic low (discharge mode), the IA gain is

inverting.

10kΩ

20kΩ

806Ω

RGP

RGN

ISVN

ISVP

+CURRENT

SHUNT

–CURRENT

SHUNT

ISMEA

–

G = 2 SUBTRACTOR

100kΩ

19.2kΩ

ISREFH

ISREFL

VREF

POLARITY

INVERTER

POLARITY

INVERTER

MODE

–

10kΩ

1667Ω

Figure 44. IA Simplified Block Diagram

IA Offset Option

As shown in Figure 44, the IA reference node is connected to

the ISREFL and ISREFH pins via an internal resistor divider.

This resistor divider can be used to introduce a temperature

insensitive offset to the output of the IA such that it always

reads a voltage higher than zero for a zero differential input.

Because the output voltage of the IA is always positive, a

unipolar analog-to-digital converter (ADC) can digitize it.

Rev. 0 | Page 18 of 32

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