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PEF80902 Fiches technique(PDF) 21 Page - Infineon Technologies AG

No de pièce PEF80902
Description  4B3T Second Gen. Modular ISDN NT(Ordinary)
PDF  83 Pages
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Fabricant  INFINEON [Infineon Technologies AG]
Site Internet  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

PEF80902 Fiches technique(HTML) 21 Page - Infineon Technologies AG

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PEF 80902
Functional Description
Data Sheet
13
2001-11-12
2
Functional Description
2.1
Reset Generation
External Reset Input
At the RST input an external reset can be applied forcing the T-SMINTâO in the reset
state. This external reset signal is additionally fed to the RSTO output.
Reset Ouput
If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by
tDEACT (see Table 28).
Reset Generation
The T-SMINTâO has an on-chip reset generator based on a Power-On Reset (POR) and
Under Voltage Detection (UVD) circuit (see Table 28). The POR/UVD requires no
external components.
The POR/UVD circuit can be disabled via pin VDDDET.
The requirements on VDD ramp-up during power-on reset are described in
Chapter 4.6.3.
Clocks and Data Lines During Reset
During reset the data clock (DCL) and the frame synchronization (FSC) keep running.
During reset DD and DU are high; with the exception of:
• The output C/I code from the U-Transceiver on DD is ’DR’ = 0000
• The output C/I code from the S-Transceiver on DU is ’TIM’ = 0000.



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