Product Description
PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM applications. This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels.

Product Features
• PLL clock distribution optimized for SSTL_2 DDR SDRAM applications.
• Distributes one differential clock input pair to five differential clock output pairs.
• Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
• Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
• External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input.
• Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers
• Available Package: – Plastic 28-pin TSSOP