Features
■ 64 MHz, single issue, 32-bit CPU core complex (e200z0h) – Compliant with Power Architecture® embedded category – Variable Length Encoding (VLE)
■ Memory organization – Up to 512 KB on-chip code flash memory with ECC and erase/program controller – Additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM emulation – Up to 40 KB on-chip SRAM with ECC
■ Fail safe protection – Programmable watchdog timer – Non-maskable interrupt – Fault collection unit
■ Nexus L2+ interface
■ Interrupts – 16-channel eDMA controller – 16 priority level controller
■ General purpose I/Os individually programmable as input, output or special function
■ 2 general purpose eTimer units – 6 timers each with up/down count capabilities – 16-bit resolution, cascadable counters – Quadrature decode with rotation direction flag – Double buffer input capture and output compare
■ Communications interfaces – 2 LINFlex channels (LIN 2.1) – 4 DSPI channels with automatic chip select generation – 1 FlexCAN interface (2.0B Active) with 32 message objects – 1 safety port based on FlexCAN with 32 message objects and up to 7.5 Mbit/s capability; usable as second CAN when not used as safety port – 1 FlexRay™ module (V2.1) with selectable dual or single channel support, 32 message objects and up to 10 Mbit/s (512 KB device only)
■ Two 10-bit analog-to-digital converters (ADC) – 2 × 11 input channels, + 4 shared channels – Conversion time < 1 µs including sampling time at full precision – Programmable ADC Cross Triggering Unit (CTU) – 4 analog watchdogs with interrupt capability
■ On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM)
■ 1 FlexPWM unit: 8 complementary or independent outputs with ADC synchronization signals