DESCRIPTION
The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave and, thus, the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.

FEATURES
■ 525ps propagation delay
■ 2.2GHz toggle frequency
■ High bandwidth output transistions
■ Internal 75KΩ input pull-down resistors
■ Available in 8-pin SOIC package