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EDS5104ABTA (128M words x 4 bits)

EDS5108ABTA (64M words x 8 bits)

EDS5116ABTA (32M words x 16 bits)

The EDS5104AB is a 512M bits SDRAM organized as 33,554,432 words ×4 bits ×4 banks. The EDS5108AB is a 512M bits SDRAM organized as 16,777,216 words ×8 bits × 4  banks.   The EDS5116AB  is  a  512M bits SDRAM  organized  as  8,388,608  words × 16  bits ×4 banks. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP (II).