General Description

These 8-bit shift registers feature gated serial inputs and n asynchronous clear. A LOW logic level at either serial input inhibits entry of the new data, and resets the first flip-flop to the LOW level at the next clock pulse, thus providing complete control over incoming data. A HIGH logic level on either input enables the other input, which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Clocking occurs on the LOW-to-HIGH level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects.



Features

■ Gated (enable/disable) serial inputs

■ Fully buffered clock and serial inputs

■ Asynchronous clear

■ Typical clock frequency 36 MHz

■ Typical power dissipation 185 mW