GENERAL DESCRIPTION The ADP7102 is a CMOS, low dropout linear regulator that operates from 3.3 V to 20 V and provides up to 300 mA of output current. This high input voltage LDO is ideal for regulation of high performance analog and mixed signal circuits operating from 19 V to 1.22 V rails. Using an advanced proprietary architecture, it provides high power supply rejection, low noise, and achieves excellent line and load transient response with just a small 1 μF ceramic output capacitor. FEATURES Input voltage range: 3.3 V to 20 V Maximum output current: 300 mA Low noise: 15 μV rms for fixed output versions PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V Reverse current protection Low dropout voltage: 200 mV at 300 mA load Initial accuracy: ±0.8% Accuracy over line, load, and temperature: −2%, +1% Low quiescent current (VIN = 5 V), IGND = 750 μA with 300 mA load Low shutdown current: 40 μA at VIN = 12 V Stable with small 1 μF ceramic output capacitor 7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 5 V, and 9 V Adjustable output from 1.22 V to VIN − VDO Foldback current limit and thermal overload protection User programmable precision UVLO/enable Power-good indicator 8-lead LFCSP and 8-lead SOIC packages APPLICATIONS Regulation to noise sensitive applications: ADC, DAC circuits, precision amplifiers, high frequency oscillators, clocks, and phase-locked loops Communications and infrastructure Medical and healthcare Industrial and instrumentation
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