▪ Flexible Power Sequencing (FPS) ensures good behavior
when powered up without input clock
▪ Power-Down Tolerant Input (PDT) inputs: SEL_A_B#, SADR0_tri, OE# pins
▪ Integrated terminations eliminate 32 resistors, saving 62mm2 of area
▪ 8 OE# pins; hardware control of each output. SMBus control also available
▪ 3 selectable SMBus addresses
▪ Spread spectrum compatible; tracks spreading input clock for
EMI reduction
▪ Maximum operating frequency of 400MHz
▪ 6 × 6 mm 48-VFQFPN package