▪ Twelve low skew, low additive jitter LVDS output pairs
▪ Two selectable, differential clock input pairs
▪ Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL, CML
▪ Maximum input clock frequency: 2GHz (maximum)
▪ LVCMOS/LVTTL interface levels for the control input select pins
▪ Output skew: 40ps (maximum)
▪ Propagation delay: 310ps (typical)
▪ Low additive phase jitter, RMS; fREF = 156.25MHz,
10kHz to 20MHz: 77fs (typical)
▪ Device current consumption (IDD): 213mA (maximum)
▪ 2.5V supply voltage
▪ Lead-free (RoHS 6), 6 6 mm, 40-VFQFN packaging
▪ -40°C to 85°C ambient operating temperature