1.1 Features
Ultra-low power consumption technology
• VDD = 2.4 to 5.5 V
(10-bit SAR A/D converter: 2.4 to 5.5 V,
operating voltage of the analog front-end
(AFE): 2.7 to 5.5 V) Note 1,
VDD = 1.8 to 5.5 VNote 2
• HALT mode
• STOP mode
• SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be
changed from high speed (0.04167 μs: @ 24
MHz operation with high-speed on-chip
oscillator clock) to ultra-low speed (30.5 μs:
@ 32.768 kHz operation with subsystem clock)
• Multiply/divide and multiply/accumulate
instructions are supported.
• Address space: 1 MB
• General-purpose registers: (8-bit register × 8)
× 4 banks
• On-chip RAM: 5.5 KBNote 1, 8 KBNote 2