Functional Description[1]
The CY7C1214H is a 32K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features
• 32K X 32 common I/O
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O power supply (VDDQ)
• Fast clock-to-output times
   — 6.5 ns (for 133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Available in JEDEC-standard lead-free 100-Pin TQFP package
• “ZZ” Sleep Mode option