Four Modes of Operation:
− Hold (Store)
− Shift Right
− Shift Left
− Load Data
Operates With Outputs Enabled or at High
Impedance
3-State Outputs Drive Bus Lines Directly
Can Be Cascaded for N-Bit Word Lengths
Direct Overriding Clear
Applications:
− Stacked or Pushdown Registers
− Buffer Storage
− Accumulator Registers

description/ordering information
These 8-bit universal shift/storage registers
feature multiplexed I/O ports to achieve full 8-bit
data handling in a single 20-pin package. Two
function-select (S0, S1) inputs and two
output-enable (OE1, OE2) inputs can be used to
choose the modes of operation listed in the
function table.
Synchronous parallel loading is accomplished by
taking both S0 and S1 high. This places the
3-state outputs in a high-impedance state and
permits data that is applied on the I/O ports to
be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in
any mode. Clearing occurs when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs
but has no effect on clearing, shifting, or storage of data.