Introduction
The SparX-5 Enterprise Ethernet switch family provides a rich set of Enterprise switching features such as
advanced TCAM-based VLAN and QoS processing enabling delivery of differentiated services, and security
through TCAM-based frame processing using versatile content aware processor (VCAP). IPv4/IPv6 Layer 3 (L3)
unicast and multicast routing is supported with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
IPv6 (S,G) multicast groups. L3 security features include source guard and reverse path forwarding (uRPF) tasks.
Additional L3 features include VRF-Lite and IP tunnels (IP over GRE/IP).
The SparX-5 switch family features a highly flexible set of Ethernet ports with support for 10G aggregation links,
QSGMII, USGMII, and USXGMII.
The device integrates a powerful 1 GHz dual-core ARM®
Cortex®
-A53 CPU enabling full management of the
switch and advanced Enterprise applications.
The SparX-5 switch family targets managed Layer 2 and Layer 3 equipment in SMB, SME, and Enterprise where
high port count 1G/2.5G/5G/10G switching with 10G aggregation links is required.
The SparX-5 switch family consists of following SKUs.
VSC7546 SparX-5-64 supports up to 64 Gbps of bandwidth with the following primary port configurations.
• 6 ×10G
• 16 × 2.5G + 2 × 10G
• 24 × 1G + 4 × 10G
VSC7549 SparX-5-90 supports up to 90 Gbps of bandwidth with the following primary port configurations.
• 9 × 10G
• 16 × 2.5G + 4 × 10G
• 48 × 1G + 4 × 10G
In addition, the device supports one 10/100/1000/2500/5000 Mbps SGMII/SerDes node processor interface
(NPI) Ethernet port.

Features
This section lists the key device features and benefits.
• Layer 2 and Layer 3 Forwarding
– IEEE®
802.1Q switch with 4K VLANs and 32K MAC table entries
– Push/pop/translate up to three VLAN tags on ingress and egress
– RSTP and MSTP support
– Fully nonblocking wire-speed switching performance for all frame sizes
– Link aggregation and DRNI per IEEE 802.1AX
– External bridge port extender role per IEEE 802.1BR
– IPv4/IPv6 unicast and multicast Layer 2 switching with up to 32K groups and 2K port masks
– IPv4/IPv6 unicast and multicast Layer 3 forwarding (routing) with reverse path forwarding (RPF) support
– IGMPv2, IGMPv3, MLDv1, and MLDv2 support
– IPv4 tunnels including GRE, 6to4, 6rd, 6over4, ISATAP, and 6in4
– Energy Efficient Ethernet (EEE) (IEEE 802.3az)
• Quality of Service
– Four megabytes of integrated shared packet memory
– Two megabytes of integrated shared packet memory
– Eight QoS classes with a pool of up to 32K queues
– TCAM-based classification with pattern matching against Layer 2 through Layer 4 information
– Dual-rate policers selected by VCAP IS2, eight dual-rate priority policers per port, and four single-rate
port policers for each port
– Flexible 4K ingress QoS mappings and 8K egress QoS mappings for VLAN tags and DSCP values
– 4K egress VLAN tag operations
– Low latency cut-through forwarding mode
– Priority-based flow control (PFC) (IEEE 802.1Qbb)
• Security
– Versatile content aware processor (VCAP™) packet filtering engine using ACLs for ingress and egress
packet inspection with four ingress lookups per frame and two egress lookups per egress frame copy
– Hierarchical VLAN ACLs and router ACLs
– Storm controllers for flooded broadcast, flooded multicast, and flooded unicast traffic
– Per-port, per-address registration for copying/redirecting/discarding
– 64 single-rate policers for ingress ACLs
– 64 single-rate policers for egress ACLs
• Management
– VCore-IV™ CPU system with integrated dual-core 1 GHz ARM Cortex-A53 CPU with MMU and DDR3/DDR4
SDRAM controller
– Integrated ARM Cortex-M3 CPU core for dedicated PCIe bootup and POE management.
– PCIe 1.x/2.0/3.0 CPU interface
– CPU frame extraction (eight queues) and injection (two queues) through DMA, which enables efficient
data transfer between Ethernet ports and CPU/PCIe
– JTAG CPU debug interface
– Configurable 32-bit data plus 8-bit ECC-capable DDR3/DDR4 SDRAM interface supporting up to eight
gigabytes (GB) of memory
– eMMC flash interface
– Sixty-four pin-shared general-purpose I/Os:
• Serial GPIO and two LED controllers controlling up to 32 ports with four LEDs each
• Triple PHY management controller (MIIM)
• Dual UART
• Dual built-in two wire serial interface multiplexer
• External interrupts
• SFP loss of signal inputs
– External access to registers through PCIe, SPI, MIIM, or through an Ethernet port with inline versatile
register access protocol (VRAP)
– Per-port counter set with support for the RMON statistics group (RFC 2819) and SNMP interfaces group
(RFC 2863)
– Support for CPU modes with internal CPU only, external CPU only, or dual CPU
• Applications
– Enterprise L2 managed and L2/L3 (L3-Lite) managed
– Enterprise edge
– WiFi aggregation
– High-end SMB/net café
– Embedded and control plane switches
– Security appliances
– Base stations and baseband processor interconnect
– Service provider CPEs