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MBM29F017A Fiches technique (PDF) - SPANSION

MBM29F017A Datasheet PDF - SPANSION
No de pièce MBM29F017A
Télécharger  MBM29F017A Télécharger

Taille du fichier   493.53 Kbytes
Page   49 Pages
Fabricant  SPANSION [SPANSION]
Site Internet  http://www.spansion.com
Logo SPANSION - SPANSION
Description FLASH MEMORY CMOS 16M (2M x 8) BIT

MBM29F017A Datasheet (PDF)

Go To PDF Page Télécharger Fiches technique
MBM29F017A Datasheet PDF - SPANSION

No de pièce MBM29F017A
Télécharger  MBM29F017A Click to download

Taille du fichier   493.53 Kbytes
Page   49 Pages
Fabricant  SPANSION [SPANSION]
Site Internet  http://www.spansion.com
Logo SPANSION - SPANSION
Description FLASH MEMORY CMOS 16M (2M x 8) BIT

MBM29F017A Fiches technique (HTML) - SPANSION

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MBM29F017A Détails du produit

■ DESCRIPTION
The MBM29F017A is a 16M-bit, 5.0 V-Only Flash memory organized as 2M bytes of 8 bits each. The 2M bytes of data is divided into 32 sectors of 64K bytes for flexible erase capability. The 8 bit of data will appear on DQ7 to DQ0. The MBM29F017A is offered in a 48-pin TSOP package. This device is designed to be programmed in system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for program or erase operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F017A offers access times between 70 ns and 120 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.
The MBM29F017A is command set compatible with JEDEC standard single-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0 V Flash or EPROM devices.

■ FEATURES
• Single 5.0 V read, write, and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standard commands
   Pinout and software compatible with single-power supply Flash
   Superior inadvertent write protection
• 48-pin TSOP, 40-pin SON
• Minimum 100,000 write/erase cycles
• High performance
   70 ns maximum access time
• Sector erase architecture
   Uniform sectors of 64K bytes each
   Any combination of sectors can be erased. Also supports full chip erase
• Embedded EraseTM Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
   Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/BUSY output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• Low VCC write inhibit ≤ 3.2 V
• Hardware RESET pin
   Resets internal state machine to the read mode
• Erase Suspend/Resume
   Supports reading or programming data to a sector not being erased
• Sector group protection
   Hardware method that disables any combination of sector groups from write or erase operation
   (a sector groupconsists of 4 adjacent sectors of 64K bytes each)
• Temporary sector groups unprotection
   Hardware method temporarily enable any combination of sectors from write or erase operations




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