GENERAL DESCRIPTION (PDL129)

The Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations.

DISTINCTIVE CHARACTERISTICS

MCP Features

■ Consists of Am29PDL127H/Am29PDL129H, 64 Mb pSRAM and two Am29LV640M.

■ Power supply voltage of 2.7 to 3.1 volt

■ High performance (XIP)

   — Access time as fast as 65 ns initial / 25 ns page

■ High performance (Data Storage)

   — Access time as fast as 110 ns initial / 30 ns page

■ Package

   — 93-Ball FBGA

■ Operating Temperature

   — –40°C to +85°C

Flash Memory Features (XIP)

AM29PDL127H/AM29PDL129H

ARCHITECTURAL ADVANTAGES

■ 128 Mbit Page Mode device

   — Page size of 8 words: Fast page read access from random locations within the page

■ Dual Chip Enable inputs (PDL129 only)

   — Two CE# inputs control selection of each half of the memory space

■ Single power supply operation

   — Full Voltage range: 2.7 to 3.1 volt read, erase, and program operations for battery-powered applications

■ Simultaneous Read/Write Operation

   — Data can be continuously read from one bank while executing erase/program functions in another bank

   — Zero latency switching from write to read operations

■ FlexBank Architecture

   — 4 separate banks, with up to two simultaneous operations per device

   PDL127:

       — Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)

       — Bank B: 48 Mbit (32 Kw x 96)

       — Bank C: 48 Mbit (32 Kw x 96)

       — Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31)

   PDL129:

       — Bank 1A: 48 Mbit (32 Kw x 96)

       — Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31)

    — Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)

       — Bank 2B: 48 Mbit (32 Kw x 96)

■ SecSiTM (Secured Silicon) Sector region

   — Up to 128 words accessible through a command sequence

   — Up to 64 factory-locked words

   — Up to 64 customer-lockable words

■ Both top and bottom boot blocks in one device

■ Manufactured on 0.13 µm process technology

■ 20-year data retention at 125°C

■ Minimum 1 million erase cycle guarantee per sector

PERFORMANCE CHARACTERISTICS

■ High Performance

   — Page access times as fast as 25 ns

   — Random access times as fast as 65 ns

■ Power consumption (typical values at 10 MHz)

   — 45 mA active read current

   — 25 mA program/erase current

   — 1 µA typical standby mode current

SOFTWARE FEATURES

■ Software command-set compatible with JEDEC 42.4 standard

   — Backward compatible with Am29F and Am29LV families

■ CFI (Common Flash Interface) complaint

   — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices

■ Erase Suspend / Erase Resume

   — Suspends an erase operation to allow read or program operations in other sectors of same bank

■ Unlock Bypass Program command

   — Reduces overall programming time when issuing multiple program command sequences

HARDWARE FEATURES

■ Ready/Busy# pin (RY/BY#)

   — Provides a hardware method of detecting program or erase cycle completion

■ Hardware reset pin (RESET#)

   — Hardware method to reset the device to reading array data

■ WP#/ACC (Write Protect/Acceleration) input

   — At VIL, hardware level protection for the first and last two 4K word sectors.