Features
• SRAM-type interface
• Double-data-rate architecture
• PLL circuitry
• Cycle time: 1.875 ns @ tRC = 15 ns
2.5 ns @ tRC = 15 ns
2.5 ns @ tRC = 20 ns
3.3 ns @ tRC = 20 ns
• Non-multiplexed addresses
• Multiplexing option is available.
• Data mask for WRITE commands
• Differential input clocks (CK and CK#)
• Differential input data clocks (DK and DK#)
• Data valid signal (QVLD)
• Programmable burst length: 2 / 4 / 8 (x9 / x18)
• User programmable impedance output (25 Ω - 60 Ω)
• JTAG boundary scan