1 General description
The 74ALVC16834A is an 18-bit registered driver. Data flow is controlled by active low
output enable (OE), active low latch enable (LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held
at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is
stored in the latch/flip-flop.
When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the state of the latch/
flip-flop.
To ensure the high-impedance state during power up or power down, OE should be tied
to VCC through a pull-up resistor; the minimum value of the resistor is determined by the
current-sinking capability of the driver.
2 Features and benefits
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low-power consumption
• Direct interface with TTL levels (2.7 V to 3.6 V)
• Current drive ± 24 mA at VCC = 3.0 V
• MULTIBYTE flow-through standard pin-out architecture
• Low inductance multiple VCC and GND pins for minimum noise and ground bounce
• Output drive capability 50 Ω transmission lines at 85°C
• Input diodes to accommodate strong drivers
• Complies with JEDEC standards:
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
– CDM JESD22-C101E exceeds 1000 V