1 Features
• AEC-Q100 qualified for automotive applications
– Temperature grade 2: –40°C to +105°C
• Functional Safety-Capable
– Documentation available to aid functional safety
system design
• Configurable high performance, low-power, frac-N
PLL with RMS jitter with spurs (12 kHz – 20 MHz,
Fout > 100 MHz) as:
– Integer mode:
• Differential output: 350 fs typical, 600 fs
maximum
• LVCMOS output: 1.05 ps typical, 1.5 ps
maximum
– Fractional mode:
• Differential output: 1.7 ps typical, 2.1 ps
maximum
• LVCMOS output: 2.0 ps typical, 4.0 ps
maximum
• Supports PCIe Gen1/2/3/4 with SSC and Gen
1/2/3/4/5 without SSC
• Internal VCO: 2.335 GHz to 2.625 GHz
• Typical power consumption: 65 mA for 4-output
channel, 23 mA for 1-output channel.
• Universal clock input, two reference inputs for
redundancy
– Differential AC-coupled or LVCMOS: 10 MHz to
200 MHz
– Crystal: 10 MHz to 50 MHz
• Flexible output clock distribution
– Four channel dividers: Up to five unique output
frequencies from 24 kHz to 328.125 MHz
– Combination of LVDS-like, LP-HCSL or
LVCMOS outputs on OUT0 – OUT4 pins
– Glitchless output divider switching and output
channel synchronization
– Individual output enable through active-low
GPIO and register
• Frequency margining options
– DCO mode: frequency increment/decrement
with 10ppb or less step-size
• Fully-integrated, configurable loop bandwidth: 100
kHz to 1.6 MHz
• Single or mixed supply for level translation: 1.8 V,
2.5 V, 3.3 V
• Configurable GPIOs and flexible configuration
options
– I2C-compatible interface: up to 400 kHz
– Integrated EEPROM with two pages and
external select pin. In-situ programming
allowed.
• Supports 100-Ω systems
• Low electromagnetic emissions
• Small footprint: 24-pin VQFN (4 mm × 4 mm)

2 Applications
• PCIe Gen 1 - Gen 5 clocking
• Advanced driver assistance systems (ADAS) -
sensor fusion
• Infotainment & cluster - automotive head unit -
eAVB
• Data center & enterprise computing
• PC & notebooks
• Enterprise machine - multifunction printer
• Test & measurement - handheld equipment

3 Description
The CDCE6214Q1TM is a 4-channel, ultra-low power,
medium grade jitter, clock generator for automotive
application that can generate five independent clock
outputs selectable between various modes of drivers.
The input source can be a single-ended or differential
input clock source, or a crystal. The CDCE6214Q1TM
features a frac-N PLL to synthesize unrelated base
frequency from any input frequency.