• Memory storage capacity:
IDT723624 – 256 x 36 x 2
IDT723634 – 512 x 36 x 2
IDT723644 – 1,024 x 36 x 2
• Clock frequencies up to 67 MHz (10 ns access time)
• Two independent clocked FIFOs buffering data in opposite directions
• Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
• Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
• Serial or parallel programming of partial flags
• Port B bus sizing of 36-bits (long word), 18-bits (word) and
9-bits (byte)
• Big- or Little-Endian format for word and byte bus sizes
• Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
• Mailbox bypass registers for each FIFO
• Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock
edge is permitted)
• Auto power down minimizes power dissipation
• Available in space saving 128-pin Thin Quad Flatpack (TQFP)
• Green parts available, see ordering information