FEATURES
• One differential 3.3V LVPECL output
• One CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum clock input frequency: 1GHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 2.1ns (maximum)
• LVPECL mode operating voltage supply range:
VCC = 3.0V to 3.465V, VEE = 0V
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package