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74ALVC164245 Fiches technique (PDF) - Nexperia B.V. All rights reserved

74ALVC164245 Datasheet PDF - Nexperia B.V. All rights reserved
No de pièce 74ALVC164245
Télécharger  74ALVC164245 Télécharger

Taille du fichier   242.93 Kbytes
Page   14 Pages
Fabricant  NEXPERIA [Nexperia B.V. All rights reserved]
Site Internet  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
Description 16-bit dual supply translating transceiver; 3-state

74ALVC164245 Datasheet (PDF)

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74ALVC164245 Datasheet PDF - Nexperia B.V. All rights reserved

No de pièce 74ALVC164245
Télécharger  74ALVC164245 Click to download

Taille du fichier   242.93 Kbytes
Page   14 Pages
Fabricant  NEXPERIA [Nexperia B.V. All rights reserved]
Site Internet  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
Description 16-bit dual supply translating transceiver; 3-state

74ALVC164245 Fiches technique (HTML) - Nexperia B.V. All rights reserved

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74ALVC164245 Détails du produit

1. General description
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to
interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The direction control inputs (1DIR and 2DIR) determine the direction of the data flow.
nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables data
from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH, disable both
nAn and nBn ports by placing them in a high-impedance OFF-state. Pins nAn, nOE and nDIR are
referenced to VCC(A) and pins nBn are referenced to VCC(B).
In suspend mode, when one of the supply voltages is zero, there will be no current flow from the
non-zero supply towards the zero supply. The nAn-outputs must be set 3-state and the voltage on
the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) ≥ VCC(A) (except in suspend mode).
2. Features and benefits
• Wide supply voltage range:
• 3 V port (VCC(A)): 1.5 V to 3.6 V
• 5 V port (VCC(B)): 1.5 V to 5.5 V
• CMOS low power consumption
• Overvoltage tolerant inputs to 5.5 V
• Direct interface with TTL levels
• IOFF circuitry provides partial Power-down mode operation
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Control inputs voltage range from 2.7 V to 5.5 V
• High-impedance outputs when VCC(A) or VCC(B) = 0 V
• Complies with JEDEC standards:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C




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