Features
▪ Six differential LVDS outputs
▪ One differential clock input pair
▪ CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
▪ Maximum output frequency: 1.7GHz
▪ Translates any single-ended input signal to LVDS levels with
resistor bias on nCLK input
▪ Output Skew: 55ps (maximum)
▪ Propagation delay: 850ps (maximum)
▪ Additive phase jitter, RMS: 0.067ps (typical)
▪ Full 3.3V or 2.5V supply
▪ -40°C to 85°C ambient operating temperature
▪ Available in lead-free (RoHS 6) package